1. Field of the Invention
Example embodiments relate to a method of manufacturing a semiconductor device. More particularly, example embodiments relate to a method of forming a spacer on a side wall of a structure of a semiconductor device.
2. Description of the Related Art
The dimensions of certain features of semiconductor devices have been greatly scaled down to meet the current demand for more highly integrated semiconductor devices. For example, the widths of features, the distances between features and the size of contacts, e.g., contact plugs, has all become considerably smaller over time. Included among such features are those formed by a conductive pattern on a substrate. A contact plug may be formed between adjacent features of the conductive pattern to connect conductive regions/elements provided on different layers of the semiconductor device.
However, it is difficult to properly form a contact plug of a semiconductor device between the features of a pattern when the features are minute and are spaced close to one another. A contact plug improperly formed between minute and closely spaced features of a conductive pattern may result in an electrical short between the contact plug and the conductive pattern. Furthermore, an improperly formed contact plug may result in a small area of contact between the contact plug and the substrate. In this case, the contact resistance between the contact plug and a substrate is so great as to adversely affect the operation/quality of the device.
For example, a self-alignment process is typically used to form contact plugs between conductive features spaced from one another by small intervals. In the self-alignment process, a spacer is formed on sidewalls of the conductive pattern, and then an insulation interlayer is formed to cover the conductive pattern and the spacer. The insulation interlayer is then etched to form a self-aligned contact whole extending to a substrate between adjacent features of the conductive pattern. With respect to the etching process, the insulation interlayer and the spacer are formed of respective materials having an etch selectivity such that the insulation interlayer is etched at a significantly greater rate than the spacer. The contact plug is then formed in the contact hole.
However, the spacer is formed by an etching process to be thin and thus ensure a sufficient area of contact between the contact plug and the substrate. In this case, i.e., the case of forming a thin spacer, the conductive pattern and the substrate are likely to be damaged while forming the spacer. As a result, the breakdown voltage between the contact plug and the conductive pattern worsens. Additionally, damage to the substrate, as mentioned above, may increase the contact resistance between the substrate and the contact plug considerably. Furthermore, source/drain regions of the substrate may be damaged, and current will leak from the damaged source/drain regions of the substrate (junction leakage current). Obviously, a semiconductor device including a damaged substrate, damaged source/drain regions and a damaged conductive pattern will have poor electrical characteristics.